1. Field of the Invention
The present invention relates to integrated circuit technology. More particularly, the present invention relates to electrostatic discharge (ESD) protection for integrated circuits.
2. Prior Art
Recently, mixed signal analog and digital integrated circuits are becoming popular. The analog input/output (I/O) pads in such integrated circuits can accept input voltages over extended ranges greater than ±10V. Designing an on-chip electrostatic discharge (ESD) protection device for extended voltage range I/O can be challenging.
For on-chip electrostatic discharge (ESD) protection circuits, the first requirement for achieving a good protection structure is to provide a low-impedance discharge current path to shunt ESD current and clamp the I/O pad voltage to safe levels without causing damage to the internal circuit. As geometry scales in integrated circuits, the size of ESD devices does not scale proportionally. This scaling decreases gate oxide breakdown voltages which makes designing ESD protection devices more challenging.
The most common ESD circuit used in CMOS technology is a grounded-gate NMOS transistor, an example of which is shown in FIG. 1. The major failure mode in such an ESD circuit is caused by non-uniform current distribution.
To increase current handling capability, Texas Instruments has proposed a scheme where the substrate is biased. An example of such as scheme is shown in FIG. 2. The floating p+ guard ring is shown by the dashed line.
The drawback of such a design is that the I/O pad cannot handle negative voltages. To handle a negative voltage, the p-well must be controlled to avoid any forward bias condition.